Micron: Time to move on to EDSFF from U.2 SSD form factor

U.2 has been the primary SSD in servers for over 10 years. Leveraging the 2.5” HDD form factor and having a connector that supports SATA, SAS and NVMe, this connector and form factor were critical to the adoption of SSDs. While there are other form factors being used in the industry, most units and bits in servers today for SSDs are U.2 and this form factor will be around for a while.

That said, new systems being produced for PCIe® 5.0 and PCIe® 6.0 have several challenges they need to overcome. These challenges make U.2 more difficult to implement compared to other options, like the EDSFF form factors, which were designed with these difficulties in mind.

Full disclosure: I am biased towards EDSFF. I spent several years working on and promoting these specifications. However, this bias comes from the precise reason why these specifications were originally developed. The storage industry needed flexible form factors with common building blocks to keep up with the diverse and rapid growth of SSD implementations in enterprise and data center for compute, storage and now AI applications.

System SI challenges:​

Figure 1 shows a typical bus topology from host port to device which is called a 3-connector topology because of the number of connectors. This topology works well with PCIe® 3.0 and 4.0 but became much more difficult to implement in PCIe® 5.0 due to the increased signaling speed impacting the signal eye (measurement determining a “1” or “0”).


Figure 1: Typical 3-connector topology used for U.2 and EDSFF

The only ways to improve the 3-connector topology are to either reduce the total topology length or use higher-cost components (PCBs, cables, re-timers, etc.). EDSFF supports Figure 1 but also supports 2-connector and 1-connector topologies, as shown in Figure 2, using an orthogonal connector. These topologies help solve this problem by removing the backplane and connectors that impact the signal eye.


Figure 2: Typical 2-connector and 1-connector topologies used for EDSFF

PCIe® 6.0 makes this challenge even more difficult because it goes from one signaling level to four signaling levels, which reduces the signaling eye to one-quarter of its original size. Not only does the problem with signaling loss become much more critical, but factors like noise between transmit and receive pairs become a bigger problem. The EDSFF connector pinout (Figure 3) isolates the transmit and receive pairs to opposite sides of the connector.


Figure 3: EDSFF pinout

The U.2 connector (Figure 4) does not have this sort of isolation. This results in higher crosstalk (called NEXT). These limitations make the U.2 a more expensive solution to implement from both an SSD and system perspective.


Figure 4: U.2 pinout

Thermal challenges:​

As more performance is required, thermal headroom to cool both the SSD and what sits behind the SSDs becomes limited. Figure 5 shows a study between the E3.S 1T and U.2. At the same power, E3.S requires less volumetric air to cool at the same capacity and power as a U.2 at various input air temperatures. This is due to a couple of factors. The E3.S 1T is smaller than U.2, so less air flow is needed to push through and around it. Also, E3.S 1T is more efficient at passing airflow through the SSD (fewer components/connectors in the way).

The argument against the E3.S is that a system could require more airflow with E3.S versus U.2 since more E3.Ss could be populated in the same space as U.2. This is a design choice though. A system could also have fewer devices and group the E3.S SSDs together to allow air to be ducted to critical components. The system could also use the orthogonal connector from Figure 2, which helps airflow. These would also greatly benefit the thermal performance of the system.


Figure 5: Thermals of E3.S 1T vs. U.2

Investment challenges:​

When EDSFF started, the participating companies knew this was a future investment. The downside is there are now two competing technologies requiring the same investment: EDSFF and U.2. The investments into systems and the ecosystem are already happening with EDSFF as specifications are in place, SSDs are being developed, and systems are planned to support EDSFF. This same investment for U.2 is not there.

Final thoughts:​

There are three phases of technology: The high initial investment/adoption cost, the sweet spot where technology improves rapidly at minimal cost and the higher cost of trying to optimize a legacy technology. EDSFF entered the technology sweet spot with PCIe® 5.0. Between the SI limitations, thermal challenges and investment challenges, U.2 left the sweet spot. My belief is that it’s time for the industry to stop investments toward U.2 and transition to the EDSFF form factors.